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datasheet 25-bit configurable registered buffer for ddr2 confidential idt74sstubf32866b 25-bit configurable registered buffer for ddr2 1 idt74sstubf32866b 7067/9 confidential description this 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-v to 1.9-v v dd operation. all clock and data inputs are compatible with the jedec standard for sstl_18. the control inputs are lvcmos. all outputs are 1.8-v cmos drivers that have been optimized to drive the ddr-ii dimm load. idt74sstubf32866b operates from a differential clock (clk and clk ). data are registered at the crossing of clk going high, and clk going low. the c0 input controls the pinout configuration of the 1:2 pinout from a configuration (when low) to b configuration (when high). the c1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high). a - pair configuration (c01 = 0, c11 = 1 and c02 = 0, c12 = 1) parity that arrives one cycle after the data input to which it applies is checked on the par_in of the first register. the second register produces to ppo and qerr signals. the qerr of the first register is left floating. the valid error information is latched on the qerr output of the second register. if an error occurs qerr is latched low for two cycles or until reset is low. b - single configuration (c0 = 0, c1 = 0) the device supports low-power standby operation. when the reset input (reset ) is low, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (v ref ) inputs are allowed. in addition, when reset is low all registers are reset, and all outputs are forced low. the lvcmos reset and cn inputs must always be held at a valid logic high or low level. to ensure defined outputs from the register before a stable clock has been supplied, reset must be held in the low state during power up. in the ddr-ii rdimm application, reset is specified to be completely asynchronous with respect to clk and clk . therefore, no timing relationship can be guaranteed between the two. when entering reset, the register will be cleared and the out puts will be driven low quickly, relative to the time to disable the differential input receivers. however, when coming out of reset, th e register will become active quickly, relative to the time to enable the differential input receivers. as long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of reset until the input receivers are fully enabled, the design of the idt74sstubf32866b must ensure that the outputs will remain low, thus ensuring no glitches on the output. the device monitors both dcs and csr inputs and will gate the qn outputs from changing states when both dcs and csr inputs are high. if either dcs and csr input is low, the qn outputs will fu nction normally. the reset input has priority over the dcs and csr control and will force the outputs low. if the dcs -control functionality is not desired, then the csr input can be hardwired to ground, in which case, the setup-time requirement for dcs would be the same as for the other d data inputs. package options include 96-ball lfbga (mo-205cc). features ? 25-bit 1:1 or 14-bit 1:2 registered buffer with parity check functionality ? supports sstl_18 jedec specification on data inputs and outputs ? supports lvcmos switching levels on c0, c1, and reset inputs ? low voltage operation: v dd = 1.7v to 1.9v ? available in 96-ball lfbga package applications ? ddr2 memory modules ? provides complete d dr dimm solution with ics98ulpa877a or idtcspua877a ? ideal for ddr2 667 and 800
idt74sstubf32866b 25-bit configurable register ed buffer for ddr2 commercial temperature grade 25-bit configurable registered buffer for ddr2 2 idt74sstubf32866b 7067/9 confidential functional block diagram for 1:1 mode (positive logic) o 1 q1a r 1d c1 reset clk clk v ref d1 dcke dodt dcs to 21 other channels csr qotda r d c1 qcsa r 1d c1 qckea r d c1 q1b (1) note: 1. disabled in 1:1 configuration.
idt74sstubf32866b 25-bit configurable register ed buffer for ddr2 commercial temperature grade 25-bit configurable registered buffer for ddr2 3 idt74sstubf32866b 7067/9 confidential functional block diagram for 1:2 mode (positive logic) reset clk clk v ref dcke dodt r 1d c1 dcs to 10 other channels (d2-d6, d8-d10, d12-d13) csr r 1d c1 r 1d c1 qcsa qcsb qodta qodtb qckea qckeb d1 q1a q1b r 1d c1 0 1 (1) note: 1. disabled in 1:1 configuration. (1) (1) (1)
idt74sstubf32866b 25-bit configurable register ed buffer for ddr2 commercial temperature grade 25-bit configurable registered buffer for ddr2 4 idt74sstubf32866b 7067/9 confidential pin configurations 14 bit 1:2 registers register a (c0 = 0, c1 = 1) 25 bit 1:1 register c0 = 0, c1 = 0 register b (c0 = 1, c1 = 1) 6 5 4 3 2 1 a qckeb qckea v dd v ref dcke ppo b q2a gnd gnd d2 nc c q3a v dd v dd d3 nc d qodtb qodta gnd gnd dodt qerr e q5a v dd v dd d5 nc f q6a gnd gnd d6 nc g c0 c1 v dd v dd par_in reset h qcsb qcsa gnd gnd clk dcs j z ol z oh v dd v dd clk csr k q8a gnd gnd d8 nc l q9a v dd v dd d9 nc m q10a gnd gnd d10 nc n q11a v dd v dd d11 nc p q12a gnd gnd d12 nc r q13a v dd v dd d13 nc t q14a v dd v ref d14 nc q2b q3b q5b q6b q8b q9b q10b q11b q12b q13b q14b 6 5 4 3 2 1 a nc qcke v dd v ref dcke ppo b q2 gnd gnd d2 d15 c q3 v dd v dd d3 d16 d nc qodt gnd gnd dodt qerr e q5 v dd v dd d5 d17 f q6 gnd gnd d6 d18 g c0 c1 v dd v dd par_in reset h nc qcs gnd gnd clk dcs j z ol z oh v dd v dd clk csr k q8 gnd gnd d8 d19 l q9 v dd v dd d9 d20 m q10 gnd gnd d10 d21 n q11 v dd v dd d11 d22 p q12 gnd gnd d12 d23 r q13 v dd v dd d13 d24 t q14 v dd v ref d14 d25 q15 q16 q17 q18 q19 q20 q21 q22 q23 q24 q25 6 5 4 3 2 1 a q1b q1a v dd v ref d1 ppo b q2a gnd gnd d2 nc c q3a v dd v dd d3 nc d q4b q4a gnd gnd d4 qerr e q5a v dd v dd d5 nc f q6a gnd gnd d6 nc g c0 c1 v dd v dd par_in reset h qcsb qcsa gnd gnd clk dcs j z ol z oh v dd v dd clk csr k q8a gnd gnd d8 nc l q9a v dd v dd d9 nc m q10a gnd gnd d10 nc n qodta v dd v dd dodt nc p q12a gnd gnd d12 nc r q13a v dd v dd d13 nc t qckea v dd v ref dcke nc q2b q3b q5b q6b q8b q9b q10b qodtb q12b q13b qckeb
idt74sstubf32866b 25-bit configurable register ed buffer for ddr2 commercial temperature grade 25-bit configurable registered buffer for ddr2 5 idt74sstubf32866b 7067/9 confidential 96 ball lfbga package attributes abcdefghjklmnprt 1 2 3 4 5 6 top view top marking a bcdefghjk lmnprt 6 5 4 3 2 1 bottom view side view
idt74sstubf32866b 25-bit configurable register ed buffer for ddr2 commercial temperature grade 25-bit configurable registered buffer for ddr2 6 idt74sstubf32866b 7067/9 confidential function table inputs 1 outputs reset dcs csr clk clk dn, dodt, dcke qn qcs qodt, qcke hll llll hll hhlh hlll or hl or h x q 0 2 q 0 2 q 0 2 hlh llll hlh hhlh hlhl or hl or h x q 0 2 q 0 2 q 0 2 hhl llhl hhl hhhh hhll or hl or h x q 0 2 q 0 2 q 0 2 hhh lq 0 2 hl hhh hq 0 2 hh hhhl or hl or h x q 0 2 q 0 2 q 0 2 lx or floating x or floating x or floating x or floating x or floating l l l 1 h = high voltage level l = low voltage level x = don?t care = low to high = high to low 2 output level before the indicated steady-state conditions were established.
idt74sstubf32866b 25-bit configurable register ed buffer for ddr2 commercial temperature grade 25-bit configurable registered buffer for ddr2 7 idt74sstubf32866b 7067/9 confidential parity and standby function table inputs 1 outputs reset dcs csr clk clk of inputs = h (d1 - d25) par_in 2 ppo qerr 3 hlx even l l h hlx odd l h l hlx even h h l hlx odd h l h hxl even l l h hxl odd l h l hxl even h h l hxl odd h l h hhh x x ppo 0 qerr 0 h x x l or h l or h x x ppo 0 qerr 0 lx or floating x or floating x or floating x or floating x or floating x or floating l h 1 h = high voltage level l = low voltage level x = don?t care = low to high = high to low data inputs = d2, d3, d5, d6, d8 - d25 when c0 = 0 and c1 = 0. data inputs = d2, d3, d5, d6, d8 - d14 when c0 = 0 and c1 = 1. data inputs = d1 - d6, d8 - d10, d12, d13 when c0 = 1 and c1 = 1. 2 par_in arrives one clock cycle after the data to which it applies when c0 = 0, and two clock cycles when c0 = 1. 3 this transition assumes qerr is high at the crossing of clk going high and clk going low. if qerr is low, it stays la tched low for two clock cycles or until reset is driven low.
idt74sstubf32866b 25-bit configurable register ed buffer for ddr2 commercial temperature grade 25-bit configurable registered buffer for ddr2 8 idt74sstubf32866b 7067/9 confidential logic diagram (1:1) parity logic diagram for 1:1 register conf iguration (positive logic); c0 = 0, c1 = 0 reset clk clk d2 - d3, d5 - d6, d8 - d25 v ref ce parity check c1 g2 h1 j1 22 a3, t3 g5 0 1 d clk r d clk r 1 0 d clk r d clk r a2 d2 ppo qerr par_in g1 clk r 2-bit counter d clk r 0 1 c0 g6 ce lps1 (internal node) 22 d2 - d3, d5 - d6, d8 - d25 lps0 (internal node) 22 d2 - d3, d5 - d6, d8 - d25 22 q2 - q3, q5 - q6, q8 - q25 ce q q q q q
idt74sstubf32866b 25-bit configurable register ed buffer for ddr2 commercial temperature grade 25-bit configurable registered buffer for ddr2 9 idt74sstubf32866b 7067/9 confidential logic diagram (1:2) parity logic diagram for 1:2 register - a configuration (positive logic); c0 = 0, c1 = 1 reset clk clk d2 - d3, d5 - d6, d8 - d14 v ref ce parity check c1 g2 h1 j1 11 a3, t3 g5 0 1 d clk r d clk r 1 0 d clk r d clk r a2 d2 ppo qerr par_in g1 clk r 2-bit counter d clk r 0 1 c0 g6 ce lps1 (internal node) 11 d2 - d3, d5 - d6, d8 - d14 lps0 (internal node) d2 - d3, d5 - d6, d8 - d14 11 ce 11 q2b - q3b, q5b - q6b, q8b - q14b 11 q2a - q3a, q5a - q6a, q8a - q14a q q q q q
idt74sstubf32866b 25-bit configurable register ed buffer for ddr2 commercial temperature grade 25-bit configurable registered buffer for ddr2 10 idt74sstubf32866b 7067/9 confidential logic diagram (1:2) parity logic diagram for 1:2 register - b configuration (positive logic); c0 = 1, c1 = 1 reset clk clk v ref ce parity check c1 g2 h1 j1 11 a3, t3 g5 0 1 d clk r d clk r 1 0 d clk r d clk r a2 d2 ppo qerr par_in g1 clk r 2-bit counter d clk r 0 1 c0 g6 ce lps1 (internal node) 11 lps0 (internal node) d1 - d6, d8 - d13 11 ce 11 q1b - q6b, q8b - q13b 11 q1a - q6a, q8a - q13a q q q q q d1 - d6, d8 - d13 d1 - d6, d8 - d13
idt74sstubf32866b 25-bit configurable register ed buffer for ddr2 commercial temperature grade 25-bit configurable registered buffer for ddr2 11 idt74sstubf32866b 7067/9 confidential absolute maximum ratings stresses greater than those listed under absolute maximum ratings ma y cause permanen t damage to the device. this is a stress rating only and functional operati on of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended per iods may affect reliability. item rating supply voltage, v dd -0.5v to 2.5v input voltage range, v i 1 1 the input and output negative voltage ratings may be exceeded if the ratings of the i/p and o/p clamp current are observed. -0.5v to 2.5v output voltage range, v o 1,2 2 this current will flow only when the output is in the high state level v o > v ddq . -0.5v to v dd + 0.5v input clamp current, i ik 50ma output clamp current, i ok 50ma continuous output clamp current, i o 50ma continuous current through each v dd or gnd 100ma package thermal impedance ( ja) 3 3 the package thermal impedance is calculated in accordance with jesd 51. 0m/s airflow 70.9 c/w 1m/s airflow 65 c/w storage temperature -65 to +150 c
idt74sstubf32866b 25-bit configurable register ed buffer for ddr2 commercial temperature grade 25-bit configurable registered buffer for ddr2 12 idt74sstubf32866b 7067/9 confidential terminal functions terminal name electrical characteristics description gnd ground input ground v dd 1.8v nominal power supply voltage v ref 0.9v nominal input reference clock z oh input reserved for future use z ol input reserved for future use clk differential input positive master clock input clk differential input negative master clock input c0, c1 lvcmos input configuration control inputs reset lvcmos input asynchronous reset input. resets registers and disables v ref data and clock differential-input receivers. csr , dcs sstl_18 input chip select inputs. disables outputs d1 - d24 output switching when both inputs are high. d1 - d25 sstl_18 input data input. clocked in on the crossing of the rising edge of clk and the falling edge of clk . dodt sstl_18 input the outputs of this register bit will not be suspended by the dcs and csr controls dcke sstl_18 input the outputs of this register bit will not be suspended by the dcs and csr controls q1 - q25 1.8v cmos data outputs that are suspended by the dcs and csr controls qcs 1.8v cmos data output that will not be suspended by the dcs and csr controls qodt 1.8v cmos data output that will not be suspended by the dcs and csr controls qcke 1.8v cmos data output that will not be suspended by the dcs and csr controls ppo 1.8v cmos partial parity output. indicates off parity of d1 - d25 par_in sstl_18 input parity input arrives one cycle after corresponding data input qerr open drain output output error bit, generated one cycle after the corresponding data output
idt74sstubf32866b 25-bit configurable register ed buffer for ddr2 commercial temperature grade 25-bit configurable registered buffer for ddr2 13 idt74sstubf32866b 7067/9 confidential operating characteristics the reset and cn inputs of the device must be held at valid levels (not floating) to ensure proper device operation. the differential inputs must not be floating unless reset is low. symbol parameter min. typ. max. units v ddq i/o supply voltage 1.7 1.9 v v ref reference voltage 0.49 * v dd 0.5 * v dd 0.51 * v dd v v tt termination voltage v ref - 0.04 v ref v ref + 0.04 v v i input voltage 0 v dd v v ih ac high-level input voltage data, csr , and pa r _ i n inputs v ref + 0.25 v v il ac low-level input voltage v ref - 0.25 v ih dc high-level input voltage v ref + 0.125 v il dc low-level input voltage v ref - 0.125 v ih high-level input voltage reset , c0, c1 0.65 * v ddq v v il low-level input voltage 0.35 * v ddq v icr common mode input range clk, clk 0.675 1.125 v v id differential input voltage 600 mv i oh high-level output current -8 ma i ol low-level output current 8 i errol qerr low level output current 25 ma t a operating free-air temperature 0 +70 c
idt74sstubf32866b 25-bit configurable register ed buffer for ddr2 commercial temperature grade 25-bit configurable registered buffer for ddr2 14 idt74sstubf32866b 7067/9 confidential dc electrical characterist ics over operating range following conditions apply unless otherwise specified: operating condition: t a = 0c to +70c, v dd = 1.7v to 1.9v. symbol parameter test conditions min. typ. max. units v ik i i = -18ma -1.2 v v oh output high voltage i oh = -6ma 1.2 v v ol output low voltage i ol = 6ma 0.5 v v errol qerr output low voltage i errol = 25ma, v dd = 1.7v 0.5 v i il all inputs v i = v dd or gnd; v dd = 1.9v -5 +5 a i dd static standby i o = 0, v dd = 1.9v, reset = gnd 100 a static operating i o = 0, v dd = 1.9v, reset = v dd , v i = v ih ( ac ) or v il ( ac ), clk = clk = v ih ( ac ) or v il ( ac ) 10 ma i o = 0, v dd = 1.9v, reset = v dd , v i = v ih ( ac ) or v il ( ac ), clk = v ih ( ac ), clk = v il ( ac ) 90 i ddd dynamic operating (clock only) i o = 0, v dd = 1.8v, reset = v dd , v i = v ih ( ac ) or v il ( ac ), clk and clk switching 50% duty cycle 210 a/clock mhz dynamic operating (per each data input) i o = 0, v dd = 1.8v, reset = v dd , v i = v ih ( ac ) or v il ( ac ), clk and clk switching 50% duty cycle. one data input switching at half clock frequency, 50% duty cycle. 1:1 mode 65 a/clock mhz/ data input 1:2 mode 120 c in data inputs v i = v ref 350mv 2 3 pf clk and clk v icr = 1.25v, v ipp = 360mv 2 3 reset v i = v dd or gnd 5
idt74sstubf32866b 25-bit configurable register ed buffer for ddr2 commercial temperature grade 25-bit configurable registered buffer for ddr2 15 idt74sstubf32866b 7067/9 confidential timing requirements over recommend ed operating free-air temperature range switching characteristics over recommended free air operating range (unless otherwise noted) symbol parameter v dd = 1.8v 0.1v units min. max. f clock clock frequency 410 mhz t w pulse duration, clk, clk high or low 1 ns t act 1 1 v ref must be held at a valid input voltage level and data inputs must be held at valid logic levels for a minimum time of t act (max) after reset is taken high. differential inputs active time 10 ns t inact 2 2 v ref , data, and clock inputs must be held at a valid input voltage levels (not floating) for a minimum time of t inact (max) after reset is taken low. differential inputs inactive time 15 ns t su setup time dcs before clk , clk , csr high; csr before clk , clk , dcs high 0.6 ns dcs before clk , clk , csr low 0.5 dodt, docke, and data before clk , clk 0.5 par_in before clk , clk 0.5 t h hold time dcs , dodt, dcke, and data after clk , clk 0.4 ns par_in after clk , clk 0.4 symbol parameter v dd = 1.8v 0.1v units min. max. f max max input clock frequency 410 mhz t pdm 1 1 design target as per jedec specifications. propagation delay, single bit switching, clk to clk to qn 1.1 1.5 ns t pdq 2 2 production test. (see production test circu it in test circuit and waveform section.) propagation delay, single -bit switching, clk / clk to qn 0.4 0.8 ns t pdmss 1 propagation delay, simultaneous switching, clk to clk to qn 1.6 ns t pd propagation delay, clk and clk to ppo 0.5 1.7 ns t lh low to high propagation delay, clk to clk to qerr 1.2 3 ns t hl high to low propagation delay, clk to clk to qerr 12.4ns t phl high to low propagation delay, reset to ppo to qn 3ns t plh low to high propagation delay, reset to qerr 3ns
idt74sstubf32866b 25-bit configurable register ed buffer for ddr2 commercial temperature grade 25-bit configurable registered buffer for ddr2 16 idt74sstubf32866b 7067/9 confidential output buffer characteristics output edge rates over recommended operating free-air temperature range parameter v dd = 1.8v 0.1v units min. max. dv/dt_r 1 4 v/ns dv/dt_f 1 4 v/ns dv/dt_ 1 1 difference between dv/dt_ r (rising edge rate ) and dv/dt_f (falling edge rate). 1v/ns
idt74sstubf32866b 25-bit configurable register ed buffer for ddr2 commercial temperature grade 25-bit configurable registered buffer for ddr2 17 idt74sstubf32866b 7067/9 confidential register timing timing diagram for sstubf32866b used as a single device; c0 = 0, c1 = 0, reset switches from l to h notes: 1.after reset is switched from low to high, all data and par_in input s signals must be set and held low for a minimum time of t actmax , to avoid false error. 2.if the data is clocked in on the n clock pulse, the qerr output signal will be generated on the n+2 clock pul se, and it will be valid on the n+3 clock pulse. n n+1 n+2 n+3 n+4 t pdm, t pdmss clk to q t su clk clk d1 - d25 parin qerr data to qerr latency clk to qerr t phl, t plh q1 - q25 t su t h t h csr dcs reset h, l, or x h or l (1) t act (1) ppo clk to ppo t pd (2) clk to qerr t phl
idt74sstubf32866b 25-bit configurable register ed buffer for ddr2 commercial temperature grade 25-bit configurable registered buffer for ddr2 18 idt74sstubf32866b 7067/9 confidential register timing timing diagram for the first sst ubf32866b used as a single d evice; c0 = 0, c1 = 0, reset held high note: 1.if the data is clocked in on the n clock pulse, the qerr output signal will be generated on the n+2 clock pulse, and it will be valid on the n+3 clock pulse. if an error occurs and the qerr output is driven low, it stays latched low for a minimum of two clock cycles or until reset is driven low.
idt74sstubf32866b 25-bit configurable register ed buffer for ddr2 commercial temperature grade 25-bit configurable registered buffer for ddr2 19 idt74sstubf32866b 7067/9 confidential register timing timing diagram for sstubf32866b used as a single device; c0 = 0, c1 = 0, reset switches from h to l note: 1.after reset is switched from high to low, all data and clock inputs signals must be set and held at valid logic levels (not floating) for a minimum time of t inactmax . clk clk csr dcs reset t inact h, l, or x h or l t rphl reset to ppo t rphl reset to q d1 - d25 parin qerr q1 - q25 (1) (1) ppo t rplh reset to qerr (1) (1) (1) (1)
idt74sstubf32866b 25-bit configurable register ed buffer for ddr2 commercial temperature grade 25-bit configurable registered buffer for ddr2 20 idt74sstubf32866b 7067/9 confidential register timing timing diagram for the first sst ubf32866b (1:2 register-a configuration) device used in a pair ; c0 = 0, c1 = 1, reset switches from lto h notes: 1.after reset is switched from low to high, all data and par_in input s signals must be set and held low for a minimum time of t actmax , to avoid false error. 2.if the data is clocked in on the n clock pulse, the qerr output signal will be generated on the n+1 clock pul se, and it will be valid on the n+2 clock pulse. . n n+1 n+2 n+3 n+4 t pdm, t pdmss clk to q t su clk clk d1 - d14 parin qerr q1 - q14 (1) (1) ppo (2) data to qerr latency clk to qerr t phl, t plh t su t h t h csr dcs reset h, l, or x h or l t act clk to ppo t pd clk to qerr t phl (not used)
idt74sstubf32866b 25-bit configurable register ed buffer for ddr2 commercial temperature grade 25-bit configurable registered buffer for ddr2 21 idt74sstubf32866b 7067/9 confidential register timing timing diagram for the first sstubf32866b (1 :2 register-a configuration) device u sed in a pair; c0 = 0, c1 = 1, reset held high note: 1.if the data is clocked in on the n clock pulse, the qerr output signal will be generated on the n+1 clock pulse, and it will be valid on the n+2 clock pulse. if an error occurs and the qerr output is driven low, it stays latched low for a minimum of two clock cycles or until reset is driven low.
idt74sstubf32866b 25-bit configurable register ed buffer for ddr2 commercial temperature grade 25-bit configurable registered buffer for ddr2 22 idt74sstubf32866b 7067/9 confidential register timing timing diagram for the first sstubf32866b (1 :2 register-a configuratio n) device used in a pair; c0 = 1, c1 = 1; reset switches from h to l note: 1.after reset is switched from high to low, all data and clock inputs signals must be set and held at valid logic levels (not floating) for a minimum time of t inactmax . clk clk csr dcs reset t inact h, l, or x h or l t rphl reset to ppo t rphl reset to q d1 - d14 parin qerr q1 - q14 (1) (1) ppo t rplh reset to qerr (1) (1) (1) (1) (not used)
idt74sstubf32866b 25-bit configurable register ed buffer for ddr2 commercial temperature grade 25-bit configurable registered buffer for ddr2 23 idt74sstubf32866b 7067/9 confidential register timing timing diagram for the se cond sstubf32866b (1:2 register-b configuration) device used in a pair; c0 = 1, c1 = 1, reset switches from l to h notes: 1.after reset is switched from low to high, all data and par_in inputs signal s must be set and held low for a minimum time of tactmax, to av oid false error. 2.par_in is driven from ppo of the first sstuaf32866 device. 3.if the data is clocked in on the n clock pulse, the qerr output signal will be generated on the n+2 clock pul se, and it will be valid on the n+3 clock pulse. nn+1n+2n+3n+4 t pdm, t pdmss clk to q t su clk clk d1 - d14 parin qerr data to qerr latency clk to qerr t phl, t plh q1 - q14 t su t h t pd t h csr dcs reset h, l, or x h or l (1) t act (1,2) ppo clk to ppo (3) clk to qerr t phl (not used)
idt74sstubf32866b 25-bit configurable register ed buffer for ddr2 commercial temperature grade 25-bit configurable registered buffer for ddr2 24 idt74sstubf32866b 7067/9 confidential register timing timing diagram for the se cond sstubf32866b (1:2 register-b configuration) device used in a pair; c0 = 1, c1 = 1, reset held high notes: 1.if the data is clocked in on the n clock pulse, the qerr output signal will be generated on the n+1 clock pulse, and it will be valid on the n+2 clock pulse. if an error occurs and the qerr output is driven low, it stays latched low for a minimum of two clock cycles or until reset is driven low. 2.par_in is driven from ppo of the first sstuaf32866 device.
idt74sstubf32866b 25-bit configurable register ed buffer for ddr2 commercial temperature grade 25-bit configurable registered buffer for ddr2 25 idt74sstubf32866b 7067/9 confidential register timing timing diagram for the first sstubf32866b (1 :2 register-a configuratio n) device used in a pair; c0 = 1, c1 = 1; reset switches from h to l note: 1.after reset is switched from high to low, all data and clock inputs signals must be set and held at valid logic levels (not floating) for a minimum time of t inactmax . clk clk csr dcs reset t inact h, l, or x h or l t rphl reset to ppo t rphl reset to q d1 - d14 parin qerr q1 - q14 (1) (1) ppo (not used) t rplh reset to qerr (1) (1) (1) (1)
idt74sstubf32866b 25-bit configurable register ed buffer for ddr2 commercial temperature grade 25-bit configurable registered buffer for ddr2 26 idt74sstubf32866b 7067/9 confidential test circuits and waveforms (v dd = 1.8v 0.1v) simulation load circuit voltage and current waveforms inputs active and inactive times voltage waveforms - pulse duration voltage waveforms - setup and hold times production-test load circuit voltage waveforms - propagation delay times voltage waveforms - propagation delay times notes: 1. c l includes probe and jig capacitance. 2. i dd tested with clock and data inputs held at v dd or gnd, and io = 0ma 3. all input pulses are supplied by generators having the following characteristics: prr 10mhz, zo = 50 , input slew rate = 1 v/ns 20% (unless otherwise specified). 4. the outputs are measured one at a time with one transition per measurement. 5. v tt = v ref = v dd /2 6. v ih = v ref + 250mv (ac voltage levels) for differential inputs. v ih = v dd for lvcmos input. 7. v il = v ref - 250mv (ac voltage levels) for differential inputs. v il = gnd for lvcmos input. 8. v id = 600mv. 9. t plh and t phl are the same as t pdm . c l =30pf r l =1k dut out r l= 100 clk inputs t l =50 t l =350ps,50 test point clk clk v dd r l =1k test point test point v dd 0v v dd /2 lvcmos reset input i dd v dd /2 t inact t act 10% 90% v icr v id v icr input t w v ref v ih v il v ref input v icr v id t su t h clk clk z o =50 test point r l =50 dut out clk inputs clk v dd /2 clk z o =50 z o =50 test point test point clk v icr v id t plh t phl output v oh v ol v icr v tt v tt clk v oh v ol v ih v il t rphl v dd /2 v tt lvcmos reset input output
idt74sstubf32866b 25-bit configurable register ed buffer for ddr2 commercial temperature grade 25-bit configurable registered buffer for ddr2 27 idt74sstubf32866b 7067/9 confidential test circuits and waveforms (v dd = 1.8v 0.1v) load circuit: high-to-l ow slew-rate adjustment voltage waveforms: high-to-low slew-rate adjustment load circuit: low-to-h igh slew-rate adjustment voltage waveforms: low-to-h igh slew-rate adjustment load circuit: error output measurements voltage waveforms: open drain output low-to-high transition time (w ith respect to reset input) voltage waveforms: open drain output high-to-low transition time (with r espect to clock inputs) voltage waveforms: open drain output low-to-high transition time (with r espect to clock inputs) notes: 1. cl includes probe and jig capacitance. 2. all input pulses are supplied by generators having the following characteristics: prr 10mhz, zo = 50 , input slew rate = 1 v/ns 20% (unless otherwise specified). c l =10pf r l =50 dut out test point v dd v oh 80% 20% v ol output dv_f dt_f c l =10pf r l =50 dut out test point v ol 20% 80% v oh output dv_r dt_r c l =10pf r l =1k dut out test point v dd v oh v cc output waveform 2 lvcmos reset input t plh v cc /2 0.15v 0v 0v v cc v icr t hl timing inputs v icr v i(pp) output waveform 1 v cc /2 v ol v oh output waveform 2 0.15v 0v v icr t hl timing inputs v icr v i(pp)
idt74sstubf32866b 25-bit configurable register ed buffer for ddr2 commercial temperature grade 25-bit configurable registered buffer for ddr2 28 idt74sstubf32866b 7067/9 confidential test circuits and waveforms (v dd = 1.8v 0.1v) load circuit: partial-parity-out load circuit load circuit: partial-parity-out voltage waveforms pr opagation delay times (with respect to clock inputs) load circuit: partial-parity-out voltage wavefo rms propagation delay times (with respect to reset input) c l =5pf r l =1k dut out test point clk v icr v i(p-p) t plh t phl output v oh v ol v icr v tt v tt clk v oh v ol v ih v il t rphl v dd /2 v tt lvcmos reset input output
idt74sstubf32866b 25-bit configurable register ed buffer for ddr2 commercial temperature grade 25-bit configurable registered buffer for ddr2 29 idt74sstubf32866b 7067/9 confidential package outline and pack age dimensions - bga package dimensions are kept current with jedec publication no. 95 seating plane 0.12 c c a b c d a1 d e top view t htyp dtyp 4321 numeric designations for horizontal grid bref cref typ -e- typ -e- d1 e1 alpha designations for vertical grid (letters i, o, q, and s not used) d e t e horiz vert total d h b c min/max min/max min/max 13.50 bsc 5.50 bsc 1.20/1.40 0.80 bsc 6 16 96 0.40/0.50 0.25/0.41 0.75 0.75 11.50 bsc 5.00 bsc 1.00/1.20 0.65 bsc 6 16 96 0.35/0.45 0.25/0.35 0.875 0.875 mo-205 10-0055c * source ref.: jedec publication 95, all dimensions in millimeters ref. dimensions ----- ball grid ----- max. note: ball grid total indicates maximum ball count for package. lesser quantity may be used.
idt74sstubf32866b 25-bit configurable register ed buffer for ddr2 commercial temperature grade 25-bit configurable registered buffer for ddr2 30 idt74sstubf32866b 7067/9 confidential ordering information xxx xx package device type bfg low profile, fine pitch, ball grid array - green 25-bit configurable registered buffer for ddr2 866b 32 double density idt xx family shipping carrier x 8 tape and reel sstubf xx temp. range 74 0c to +70c (commercial)
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